The present invention relates generally to semiconductor device manufacturing, and, more particularly, to a method and structure for defect monitoring of semiconductor devices using power bus wiring grids.
In the semiconductor integrated circuit (IC) industry, there is a continuing demand for higher circuit packing densities. This demand of increased packing densities has in turn led the semiconductor industry to develop new materials and processes to achieve sub-micron device dimensions. Because manufacturing ICs at such minute dimensions adds more complexity to circuits, the demand for improved methods to inspect the integrated circuits in various stages of their manufacture is ever present.
Although inspection of such products at various stages of manufacture is desirable and can significantly improve production yield and product reliability, the increased complexity of ICs increases the cost of such inspections, both in terms of expense and time. However, if a defect can be detected early in production, the cause of the defect can be determined and corrected before a significant number of defective ICs are manufactured. In this regard, defect-detecting systems frequently employ charged particle beams for a “voltage contrast” inspection technique in which a charged particle beam, such as an electron beam, is irradiated on certain defect test structures.
The interaction of the electron beam with features in the circuitry generates a number of signals in varying intensities, such as secondary electrons, back-scattered electrons, x-rays, etc. The voltage contrast inspection technique operates on the principle that potential differences in the various locations of a test structure under examination cause differences in secondary electron emission intensities. Thus, the potential state of the scanned area is acquired as a voltage contrast image such that a low potential portion of, for example, a wiring pattern might be displayed as bright (i.e., the intensity of the secondary electron emission is high) and a high potential portion might be displayed as dark (i.e., lower intensity secondary electron emission). Alternatively, the system may be configured such that a low potential portion might be displayed as dark and a high potential portion might be displayed as bright.
A secondary electron detector is used to measure the intensity of the secondary electron emission that originates only at the path swept by the scanning electron beam. Thus, a defective portion of the IC may be identified from the potential state of the portion under inspection. In one form of voltage contrast inspection, the mismatched portion between the defective voltage contrast image and the defect free contrast image reveals the defect location. Alternatively, an ion beam may be used, wherein the defects from the inspection are (more generally) revealed through charge contrast.
Typically, in order to facilitate the charge contrast inspection process, manufacturers fabricate semiconductor defect test structures specifically dedicated for the defect analysis. These defect test structures are fabricated such that they are sensitive to defects that occur in IC product, but are designed so that the presence of defects is more readily ascertained. However, such defect test structures are conventionally constructed within the kerf area of the silicon wafer instead of the product die, and therefore the defect density measurements do not necessarily correlate as well to actual defect conditions on the product die. On the other hand, using the product die itself to construct inspection test structures reduces the available area on the die for the actual IC structures themselves.
Accordingly, it would be desirable to be able to implement an effective defect monitoring method as each wiring layer is formed, and in a manner that uses less silicon area than traditional kerf-based defect monitors.